fx2spiflash.h¶
The fx2spiflash.h
header contains templated 25C-compatible SPI flash routines for the Cypress FX2 series. This header is the complete implementation of the SPI flash interface and does not have a corresponding library.
Reference¶
Defines
-
SPIFLASH_WIP¶
Write-in-Progress status register bit.
-
SPIFLASH_WEL¶
Write Enable Latch status register bit.
-
DEFINE_SPIFLASH_FNS(name, cs, sck, si, so)¶
This macro defines a number of functions that implement common operations on 25C-compatible SPI flashes. They are optimized and run at ~5 MHz SCK frequency at 48 MHz CLKOUT. The
cs
,sck
,so
, andsi
parameters may point to any pins, and are defined in the formatPxn
.The defined routines are:
void name_init()
, to set outputs to their idle state. (Note that output enables must be configured by the user before callingname_init
.)void name_rdp()
, to leave deep power-down mode (commandAB
).void name_dp()
, to enter deep power-down mode (commandB9
).void name_read(uint32_t addr, __xdata uint8_t *data, uint16_t length)
, to read data at the given address, with wraparound at array boundary (command03
).void name_wren()
, to latch the write enable bit (command06
).uint8_t name_rdsr()
, to read the status register (command05
).void name_ce()
, to erase the entire chip (command60
).void name_se(uint32_t addr)
, to erase a sector at the given address (command20
).void name_pp(uint32_t addr, const __xdata uint8_t *data, uint16_t length)
, to program up to a whole page at the given address, with wraparound at page boundary (command02
).
For example, invoking the macro as
DEFINE_SPIFLASH_FNS(flash, PA0, PB0, PB1, PB2)
defines the routinesvoid flash_init()
,void flash_read()
, etc that assume an SPI flash’s CS# pin is connected to A0, SCK pin is connected to B0, MISO pin is connected to B1, and MOSI pin is connected to B2.